1. Field of the Invention
The present invention relates to a CMOS image sensor. More specifically, the present invention relates to a CMOS image sensor and a method for manufacturing the same, capable of improving characteristics of the image sensor by reducing a leakage current of a floating diffusion area.
2. Description of the Related Art
In general, an image sensor is a semiconductor device for converting optical images into electric signals, and it may be classified as a charge coupled device (CCD) or a CMOS image sensor.
The CCD has a plurality of photodiodes (PDs), which are arranged in the form of a matrix in order to convert optical signals into electric signals. The CCD includes a plurality of vertical charge coupled devices (VCCDs) provided between photodiodes and vertically arranged in the matrix so as to transmit electric charges in the vertical direction when the electric charges are generated from each photodiode, a plurality of horizontal charge coupled devices (HCCDs) for transmitting the electric charges from the VCCDs in the horizontal direction, and a sense amplifier for outputting electric signals by sensing the electric charges being transmitted in the horizontal direction.
However, CCDs may have various disadvantages, such as a complicated drive mode, high power consumption, and so forth. Also, the CDD is generally manufactured using multi-step photo processes, so the manufacturing process for the CCD can be complicated.
In addition, since it can be difficult to integrate certain circuits, such as a controller, a signal processor, and an analog/digital converter (A/D converter) onto a single chip of the CCD, the CCD may not be advantageous for compact-size products.
Recently, the CMOS image sensor has been spotlighted as a next-generation image sensor capable of solving certain problems of the CCD.
The CMOS image sensor is a device employing a switching mode to sequentially detect an output of each unit pixel using MOS transistors, in which the MOS transistors are formed on a semiconductor substrate corresponding to the unit pixels through a CMOS technology. CMOS image sensors may also use peripheral circuits or devices, such as a controller and a signal processor.
That is, the CMOS sensor includes a photodiode and at least one MOS transistor in each unit pixel, and sequentially detects the electric signals of each unit pixel in a switching mode to realize images.
Since the CMOS image sensor makes use of the CMOS technology, the CMOS image sensor has advantages such as relatively low power consumption and a relatively simple manufacturing process with fewer photo processing steps.
In addition, the CMOS image sensor allows the product to have a compact size, because peripheral circuits such as a controller, signal processor, and A/D converter can be integrated onto the CMOS image sensor chip.
Therefore, CMOS image sensors have been extensively used in various applications, such as digital still cameras, digital video cameras, and so forth.
Meanwhile, the CMOS image sensors are classified into 3T type, 4T type, and 5T type CMOS image sensors according to the number of transistors per unit pixel. The 3T type CMOS image sensor includes one photodiode and three transistors per unit pixel, and the 4T type CMOS image sensor includes one photodiode and four transistors per unit pixel.
Hereinafter, description about the layout of a unit pixel of the 4T type CMOS image sensor will be given.
FIG. 1 is a circuit diagram of a conventional four transistor (4T) CMOS image sensor.
As shown in FIG. 1, a unit pixel 100 of the CMOS image sensor includes a photo diode 10 serving as an optical-electric converter and four transistors.
The four transistors include a transfer transistor 20, a reset transistor 30, a drive transistor 40, and a select transistor 50. In addition, a load transistor 60 is electrically connected to an output terminal OUT of each unit pixel 100.
In FIG. 1, FD, Tx, Rx, Dx, and Sx denote a floating diffusion area, a gate voltage of the transfer transistor 20, a gate voltage of the reset transistor 30, a gate voltage of the drive transistor 40, and a gate voltage of the select transistor 50, respectively.
FIG. 2 is a layout view showing the unit pixel of the conventional 4T CMOS image sensor, and FIG. 3 is a sectional view taken along line II-II′ of FIG. 2 showing the conventional CMOS image sensor. FIG. 1 is a circuit schematic that is equivalent to the layout of FIG. 2.
As shown in FIGS. 2 and 3, the conventional 4T CMOS image sensor includes a P-well area 32, which is formed in a predetermined portion of a surface of a P type semiconductor substrate 31 on which an active area and an isolation area are defined, an isolation layer 34, which is formed in the isolation area of the semiconductor substrate 31, gate electrodes 23, 33, 43, and 53 of the four transistors, which are formed in the active area of the semiconductor substrate 31 with a gate insulating layer 35 between the gate electrodes and the active area, and a photodiode (PD) area, which is formed at one side of the gate electrode of the transfer transistor.
In other words, the transfer transistor 20 (see, FIG. 1), the reset transistor 30 (see, FIG. 1), the drive transistor 40 (see, FIG. 1), and the select transistor 50 (see, FIG. 1) include the gate electrodes 23, 33, 43, and 53, respectively.
High-density n+ type dopants are implanted into the active area of each transistor, except for the photodiode (PD) area and the parts of the substrate below the gate electrodes 23, 33, 43, and 53, with the same implantation depth, so that an N+ type diffusion area 36 (i.e., the source/drain areas of each transistor) is formed in the active area of each transistor.
Meanwhile, although they are not explained, reference character A represents an area where the N+ type diffusion area 36 is formed, and reference character B represents an area where the P-well area 32 is not formed.
Therefore, the FD area and the PD area are formed on the surface of the P type semiconductor substrate 31 instead of the P-well area 32.
In addition, the density of the P type semiconductor substrate 31 is within a range of 1E15/cm3 to 1E16/cm3, the density of the P-well area 32 except for the P type semiconductor substrate 31 is within a range of 1E17/cm3 to 1E18/cm3, and the density of the N+ diffusion area 36 is within a range of 1E20/cm3 to 1E22/cm3.
Meanwhile, the gate electrode 33 shown in FIG. 3 is a gate electrode of the reset transistor, and the N+ diffusion area 36 between the gate electrode 23 of the transfer transistor and the gate electrode 33 of the reset transistor is the FD area.
In addition, the bold solid line represents a connection line between the FD area and the drive transistor 40 (see, FIG. 1).
Since the P-well areas 32 in pixel areas have uniform density, the conventional CMOS image sensor has the same leakage current in the pixel areas and the same junction capacitance for a unit area.
However, it is very important to reduce a junction leakage current of an FD area in a CMOS image sensor having a structure of four (or more) transistors and one photodiode. This is because the potential of a FD area serves as the input potential of the drive transistor.
However, although the FD has no problem when a small number of electrons are carried from the photodiode, the FD cannot receive all carried electrons when a great amount of electrons are carried to the FD area (that is, when a large quantity of electrons are generated due to a great amount of light incident onto the photodiode) because the capacitor in the FD area has a relatively small capacitance.
That is, since the doping density of the P-type substrate is within a range of 1E15/cm3 to 1E16/cm3, a capacitance value of the FD area is reduced.
Accordingly, since it is difficult to receive a large amount of electrons from the photodiode, the exact potential cannot be applied to the drive transistor, so that a data failure or error may occur.